Hatim Kanchwala

Adieu, Google Summer of Code 2017

The Google Summer of Code 2017 is now in its final stages, and I’d like to take a moment to look back at what goals I accomplished, what remains to be realised and what I learned.

The EDSAC Museum on FPGA project is part of a broader movement to revive interest in the early first generation British computer, the Electronic Delay Storage Automatic Calculator. 2017 will mark the 60th anniversary of the British Computing Society (BCS) whose founder, Maurice Wilkes, is the designer of the original EDSAC.

My GSoC project’s primary objective was to replicate the EDSAC on a FPGA. All of the work I did over the summer is hosted at librecores/gsoc-museum-edsac GitHub repository. The FPGA of choice was the open source and affordable board, called myStorm. It is equipped with a Lattice ICE40HX4K FPGA and an ARM Cortex M3 microcontroller. It is really like the Raspberry Pi or the Arduino of the FPGA world!

Even though the GSoC period is coming to a conclusion, the project is still very much a work-in-progress. I had set out with a rather ambitious set of project goals in my original proposal of which only a subset was actually realised in the prescribed time period. I guess when working with hardware, one can’t really anticipate timelines with much certainty! Nonetheless, significant lessons in project management and risk assessment/mitigation were learned.

My mentor, @jeremypbennett, required me to maintain a schedule and a risk register from the start of the coding period. The schedule contained a table of work packages, planned and actual start and end dates. The work packages were supposed to be independent atomic tasks. The risk register was another table where possible risks, their likelihood of occurrence and their impact on the project were monitored. Once in every two weeks, my mentors, @jeremypbennett and @wallento, and I had a Hangouts session to discuss the schedule, assess and plan mitigation strategies for risks. This is really lightweight project management but goes a long way to ensure predictability and control.

As of this post, the EDSAC replica works in simulation. Almost all logic modules have been coded to follow the original architecture as closely as possible - the directory structure, module hierarchy, signal definitions and data flow. Most of EDSAC replica’s subsystems work independently on the myStorm board and have been tested on the board as well. A secondary goal of the project was to develop external interfaces that communicated to the FPGA over a standardised communication protocol. I gave these external interfaces a fancy name, I/O flavours. The communication protocol is developed, but the Verilog implementation and physical manufacturing of the hardware remains a task to be done. The detailed build instructions and toolchain installation instructions can be found in the project’s README.md.

This GSoC has come to the sweetest of ends one can hope for - I have the distinct pleasure of presenting at ChipHack EDSAC and ORConf this year which are being held from 6 to 10 Sept. in Hebden Bridge, UK as part of the Wuthering Bytes festival. ChipHack EDSAC is being organised by @Embecosm and ORConf by @FossiFoundation. Thanks are due to @Embecosm and @FossiFoundation for sponsoring me without which I would have certainly missed this lifetime opportunity. I am indebted to them. Looking forward to meeting some awesome people at ChipHack EDSAC and ORConf this year!

The primary channel for communication is over at Gitter. If you prefer mail, the LibreCores discussion mailing list is the central place, and I am personally available at [email protected]. Please drop by if you have questions or are interested in contributing to the project. I’d be delighted to hear from you. If you notice any bugs or would like to suggest improvements, please do open an issue. The project will remain active for long after GSoC concludes.

I’d also recommend that you visit the myStorm forum. It is the most informative place to learn, track and discuss the development of the myStorm board. They are very helpful and responsive, and I hope myStorm reaches a broad global audience.

This post is incomplete without expressing gratitude to my mentors @jeremypbennett and @wallento. They have been most kind, patient and generous in offering me time, have been very encouraging whenever I panicked or was under pressure. Dear mentors, I am indelibly indebted to you!

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