EDSAC FPGA Community Bonding Period and Coding Kickoff
Last week the Community Bonding Period of GSoC concluded, and we are now into the first phase of the Coding Period. It was an exciting one month of Community Bonding full of learning and meeting new people from around the world. The Community Bonding Period is primarily a preparatory phase for the students to define clearer project milestones, fine tune timelines, learn about organisation’s processes, fix coding practices, and set up channels for communication.
This period is also for the students to get to know the community they are now a part of - their mentors, their organisation, other GSoC-ers - and arguably that’s the most fun part! I met a couple of interesting people on the unofficial GSoC 2017 Telegram group. They were from diverse cultural backgrounds, and it was quite a delightful experience talking with them.
Most of my time during the Community Bonding Period was spent in studying EDSAC in even more depth. Soon after, I prepared plans for the coming months based on lightweight project management techniques my mentor introduced me to. Milestones are broken down into actionable tasks with a turnaround time of 1-3 days. These tasks are bundled into mini-milestones with a resolution of 5-15 days. A “risk register” is prepared to list probable risks, their likelihood of occurrence, impact on project and mitigation strategies.
Project management practices are generally perceived as cumbersome and unproductive (because from a programmer’s point of view no code is produced). From what I am experiencing now, I am pretty convinced that regularly investing bite-sized chunks of time and effort into proper planning (perhaps for shorter horizons) is a productive activity that leads to higher confidence and serves as an umbrella on a rainy day.
My mentors, @jeremypbennett and @wallento, and I had a few Hangouts meetings, we have one every two weeks. It was a pleasant meeting principally focused on work, but sprinkled with informal cultural exchanges. This is one aspect of open-source and GSoC that I absolutely love - it brings together people willing to learn and transcends cultural and geographical boundaries!
A couple of days ago the open-source myStorm “BlackIce” FPGA board arrived. My mentor shipped it from his office in London along with a kind note. The myStorm FPGA board is a low-cost development platform aimed at engineers, hobbyists and electronics students. It uses a Lattice ICE40HX4K FPGA along with a supporting ARM microcontroller. It’s designed to be used with Clifford Wolf’s ICE Storm toolset. I am quite thrilled that BlackIce will be a modern home to a reimagined EDSAC!
A sizeable chunk of my Community Bonding time was spent watching video recordings of talks at ORCONF 2016. “Formal Verification with Yosys-SMTBMC” and “LibreCores CI” are top among my favourites with “Cocotb” and “FuseSoc” following closely. Two challenges in the EDSAC FPGA Museum project that have always intrigued me are - (a) how do I verify that my replica is correct, and (b) since documentation on EDSAC is sparse, how do I write automated tests. So, I was naturally attracted to formal verification and LibreCores CI. During a Gitter session, @wallento pointed me to Cocotb. I hope I get a chance to learn and use these technologies in my GSoC project.
I currently have most of EDSAC’s functional logic mapped, and corresponding stub modules in Verilog are ready. I have partitioned these modules hierarchically into three levels -
- L3 Atomic Modules: fundamental blocks using which higher levels are built,
- L2 Logic Modules: blocks that are the crux of the machine, and
- L1 Subsystems: ALU, control section, memory and I/O.
The L3 atomic modules have been coded and simulated using iverilog and GTKWave. Initial documentation includes a description of the Instruction Set and control signals. A few L2 modules have also been coded and simulated.
For the next few weeks, my objective is to build the remainder of L2 modules making up the ALU, Control Section and Memory L1 Subsystems. I will then move on to developing a rudimentary external I/O hardware with off-the-shelf electronic components. The objective is to have a bare bones replica of EDSAC based on a functional specification. To verify the initial correctness of my FPGA model, I will take the route Prof. Martin Campbell-Kelly took with his EDSAC simulator - validate against some of the five original programs, for which both the instructions and photographs of the output exist in physical form.
You can follow my work progress at librecores/gsoc-museum-edsac. We use Gitter as our primary mode of communication. If you’d like to get in touch, you are invited to join librecores/gsoc-museum-edsac on Gitter, or if you prefer mail, then I’d be delighted to receive you at [email protected].